1. Field of the Invention
The present invention relates to a clock distribution circuit, a semiconductor integrated circuit, a method and a program for designing a clock distribution circuit.
2. Description of Related Art
A semiconductor integrated circuit (LSI) is provided with a clock distribution circuit that receives a clock from the outside and supplies the clock to a circuit requiring the clock in the semiconductor integrated circuit. The clock distribution circuit includes clock distribution interconnections and clock distribution buffers, and is configured such that clock distribution delay times from a clock supply source (clock source) to respective clock supply destinations (leafs) become uniform. A clock tree synthesis (CTS) method is used as a method for designing such the clock distribution circuit. The clock tree synthesis method has the following feature. That is, based on circuit connection information, placement information and so on, the clock from the clock source is branched into a plurality of clock lines and a clock skew is reduced by inserting buffers (also called “CTS buffers”) such that the clock delays from the clock source to respective tree end points as the branch destinations become uniform.
Japanese Laid-Open Patent Application JP-P2004-241699 discloses an example of a method of designing a clock distribution circuit by using the above-mentioned CTS method. A delay ratio between a delay of a gate of a clock distribution buffer on a clock tree and a delay of a clock distribution interconnection is calculated, and the delay ratio and a delay time are made uniform between respective clock lines, thereby reducing fluctuation in response to change in temperature or voltage.
Also, Japanese Laid-Open Patent Application JP-P2004-15032 discloses an equivalent circuit of a clock distribution circuit, which is shown in FIG. 1. In FIG. 1, a clock input buffer 2 supplies an external clock signal to a plurality of PLL circuits 1. Each PLL circuit 1 outputs the clock signal to a clock tree including a clock interconnection 5 and a clock driver 6. The clock tree distributes and supplies the clock signal to a plurality of macros 3. Each macro 3 includes an intra-macro F/F 12. A feedback circuit consisting of an interconnection 11 and an input buffer delay compensation circuit 8 is formed between an interface macro feedback clock output terminal 10 of the macro 3 and a PLL feedback clock input terminal 13 of the PLL circuit 1. That is to say, the PLL circuit 1 modulates the phase of the clock signal fed back from the macro 3 on the basis of the external clock signal and outputs to the clock tree.
The inventor of the present application has recognized the following points.
As shown in FIG. 1, the clock distribution circuit has the plurality of PLL circuits 1, and a clock tree or a clock distribution network is constructed with respect to each PLL circuit 1. The clock is fed back from the macro 3 that is the end point of the clock tree or the clock distribution network to the corresponding PLL circuit 1. However, the feedback circuit to the PLL circuit 1 is formed with disregard to a data transfer path connecting between sequential circuits that belong to different clock trees (clock domains) respective of which PLL circuits 1 as the clock supply sources are different from each other. In the present specification, the data transfer path, which connects between sequential circuits belonging to different clock trees (clock domains) respective of which PLL circuits as the clock supply sources are different from each other, is referred to as an “inter-clock-domain data transfer path” or an “inter-domain data transfer path”. For example, in the lower part of FIG. 1, the interconnection 11a and the input buffer delay compensation circuit 8a are formed as the feedback circuit to the PLL circuit 1a and also the interconnection 11b and the input buffer delay compensation circuit 8b are formed as the feedback circuit to the PLL circuit 1b, with disregard to whether or not an inter-clock-domain data transfer path connecting between the macro 3a and the macro 3b belonging to different clock trees is present.
In this case, in the clock distribution circuit shown in FIG. 1, the clock is distributed from the PLL circuit 1a to the macros 3 and 3a with the same delay, and the PLL circuit 1a adjust the phase of the output clock such that the phase of the clock (reference clock) input from the outside of the LSI to the PLL circuit 1a through the clock input buffer 2 is synchronized with the phase of the clock (feedback clock) fed back from the feedback clock output terminal 10 of the macro 3a to the PLL circuit 1a through the input buffer delay compensation circuit 8. The same applies to the PLL circuit 1b. Since the clocks are fed back from respective macros 3a and 3c as representative points to respective PLL circuits 1a and 1b, the clocks in phase and with no skew are input as the input clocks to respective macros 3a and 3c. If the clock is distributed from the PLL circuit 1a to the macros 3 and 3a with the same delay, it eventually results in the clock distribution circuit in which the phases of the input clocks of the macros 3, 3a, 3b and 3c are synchronized with the phase of the clock input to the clock input buffer 2.
Here, let us consider a case where a data transfer path exists between the macro 3a and the macro 3b. In an actual semiconductor integrated circuit, an OCV (On Chip Variation) such as variations of devices and interconnections in a chip occurs, even if circuits are so designed as to have the same circuit characteristics. Therefore, there is a possibility that the delay to the macro 3c and the delay to the macro 3b become different from each other due to influence of the OCV. This cannot be avoided even by the use of the technique described in the former patent document (Japanese Laid-Open Patent Application JP-P2004-241699). In the configuration of the clock distribution circuit shown in FIG. 1, the clock output from the PLL circuit 1b passes through the buffer 6, and is distributed to respective macros 3c and 3b via a branch node at the output of the buffer 6. According to such the circuit, the delay from the branch node to the macro 3c and the delay from the branch node to the macro 3b may become different from each other (clock skew occurs) due to the influence of the OCV. In this case, the phase of the clock signal of the macro 3a deviates from the phase of the clock signal of the macro 3b, and thus the timing of data transfer between the macro 3a and the macro 3b may become out of synchronization. As a result, the data transfer between the macro 3a and the macro 3b may possibly fail, which causes malfunction. A technique is desired that can distribute the clock signal without influenced by the OCV even in the case where the data transfer path (inter-domain data transfer path) which connects between circuits belonging to different clock trees (clock domains) exists.